The “tile”/cellular-automaton model comes from Cavin et al., “Science and Engineering Beyond Moore’s Law” (2012) and its references, particularly those by Cavin and Zhirnov, including Shankar et al. (2009) for a “detailed treatment”. As @spxtr says in a comment somewhere in the long thread, these papers are fine, but don’t mean what Jacob Cannell takes them to mean.
That detailed treatment does not describe energy demands of interconnects (the authors assume “no interconnections between devices” and say they plan to extend the model to include interconnect in the future). They propose the tiling framework for an end-of-scalingprocessor, in which the individual binary switches are as small and as densely packed as possible, such that both the switches and interconnects are tile-scale.
The argument they make in other references is that at this limit, the energy per tile is approximately the same for device and interconnect tiles. This is a simplifying assumption based on a separate calculation, which is based on the idea that the output of each switch fans out: the output bit needs to be copied to each of around 4 new inputs, requiring a minimum length of interconnect. They calculate how many electrons you need along the length of the fan-out interconnect to get >50% probability of finding an electron at each input. Then they calculate how much energy that requires, finding that it’s around the minimal switching energy times the number of interconnect tiles (e.g. Table 28.2 here).
For long/”communication” interconnects, they use the same “easy way” interconnect formula that Steven Byrnes uses above (next page after that table).
The confusion seems to be that Jacob Cannell interprets the energy per tile as a model of signal propagation, when it is a simplifying approximation that reproduces the results of a calculation in a model of signal fan-out in a maximally dense device.
The “tile”/cellular-automaton model comes from Cavin et al., “Science and Engineering Beyond Moore’s Law” (2012) and its references, particularly those by Cavin and Zhirnov, including Shankar et al. (2009) for a “detailed treatment”. As @spxtr says in a comment somewhere in the long thread, these papers are fine, but don’t mean what Jacob Cannell takes them to mean.
That detailed treatment does not describe energy demands of interconnects (the authors assume “no interconnections between devices” and say they plan to extend the model to include interconnect in the future). They propose the tiling framework for an end-of-scaling processor, in which the individual binary switches are as small and as densely packed as possible, such that both the switches and interconnects are tile-scale.
The argument they make in other references is that at this limit, the energy per tile is approximately the same for device and interconnect tiles. This is a simplifying assumption based on a separate calculation, which is based on the idea that the output of each switch fans out: the output bit needs to be copied to each of around 4 new inputs, requiring a minimum length of interconnect. They calculate how many electrons you need along the length of the fan-out interconnect to get >50% probability of finding an electron at each input. Then they calculate how much energy that requires, finding that it’s around the minimal switching energy times the number of interconnect tiles (e.g. Table 28.2 here).
For long/”communication” interconnects, they use the same “easy way” interconnect formula that Steven Byrnes uses above (next page after that table).
The confusion seems to be that Jacob Cannell interprets the energy per tile as a model of signal propagation, when it is a simplifying approximation that reproduces the results of a calculation in a model of signal fan-out in a maximally dense device.