The Information claims Nvidia is considering 192⁄256 GB of HBM capacity per chip for Rubin Ultra (released late 2027, buildout over 2028). This is in contrast with the current (non-Ultra) Rubin that has 288 GB per chip (buildout mostly completes over 2027). The implied technology is 8-Hi stacks of either HBM4E (giving 256 GB, 4 GB per DRAM die in 8 stacks per chip) or HBM4 (giving 192 GB, a direct downgrade from 12-Hi HBM4 in Rubin; this stays at 3 GB per DRAM die).
So either this is about something like a weird stripped down Meta Recsys design (Nvidia edition, following Meta’s take on AMD) unrelated to the standard version of Rubin Ultra, or at least a 2x Oberon scale-up system will be available for Rubin Ultra (so that HBM capacity still goes up compared to Rubin when counted per scale-up system). Still, that only puts a 2x Oberon system for Rubin Ultra at 28⁄37 TB of total HBM capacity (compared to the preceding year’s 21 TB in Rubin, and 31 TB in AMD MI455X Helios; presumably AMD’s scale-up system for the 2028 buildout won’t get smaller). TPU 8i (most of the buildout completes over 2027) already has 295 TB per pod, its scale-up topology is more friendly to all-to-all communications crucial for MoE decode compared to the previous TPUs, and the recent shake-up at Alphabet and GDM makes it more likely the availability of TPUs will increase for big external customers (presumably there’ll be some kind of TPU v9 for the 2028 buildout that’s even better).
Thus if Kyber isn’t coming for Rubin Ultra, and also if the 192⁄256 GB per chip are about the standard design (both premises being somewhat shaky), then it’s likely that at least a 4x Oberon scale-up system will be available for Rubin Ultra (55/74 TB of HBM per pod), possibly even 8x Oberon that was announced in Mar 2026 (111/147 TB of HBM per pod).
The Information claims Nvidia is considering 192⁄256 GB of HBM capacity per chip for Rubin Ultra (released late 2027, buildout over 2028). This is in contrast with the current (non-Ultra) Rubin that has 288 GB per chip (buildout mostly completes over 2027). The implied technology is 8-Hi stacks of either HBM4E (giving 256 GB, 4 GB per DRAM die in 8 stacks per chip) or HBM4 (giving 192 GB, a direct downgrade from 12-Hi HBM4 in Rubin; this stays at 3 GB per DRAM die).
So either this is about something like a weird stripped down Meta Recsys design (Nvidia edition, following Meta’s take on AMD) unrelated to the standard version of Rubin Ultra, or at least a 2x Oberon scale-up system will be available for Rubin Ultra (so that HBM capacity still goes up compared to Rubin when counted per scale-up system). Still, that only puts a 2x Oberon system for Rubin Ultra at 28⁄37 TB of total HBM capacity (compared to the preceding year’s 21 TB in Rubin, and 31 TB in AMD MI455X Helios; presumably AMD’s scale-up system for the 2028 buildout won’t get smaller). TPU 8i (most of the buildout completes over 2027) already has 295 TB per pod, its scale-up topology is more friendly to all-to-all communications crucial for MoE decode compared to the previous TPUs, and the recent shake-up at Alphabet and GDM makes it more likely the availability of TPUs will increase for big external customers (presumably there’ll be some kind of TPU v9 for the 2028 buildout that’s even better).
Thus if Kyber isn’t coming for Rubin Ultra, and also if the 192⁄256 GB per chip are about the standard design (both premises being somewhat shaky), then it’s likely that at least a 4x Oberon scale-up system will be available for Rubin Ultra (55/74 TB of HBM per pod), possibly even 8x Oberon that was announced in Mar 2026 (111/147 TB of HBM per pod).