Yes, but how much of the work that goes into the next generation is just layout? It doesn’t solve all of your chemical or quantum mechanical issues, or fixes your photomasks for the next shrunken generation, etc. If layout were a major factor, we should expect to hear of ‘layout farms’ or supercomputers or datacenters devoted devoted to the task. I, at least, haven’t. (I’m sure Intel has a datacenter or two, but so do many >billion tech multinationals.)
And if layout is just a fraction of the effort like 10%, then Amdahl’s law especially applies.
it doesn’t give many actual current details, but http://en.wikipedia.org/wiki/Computational_lithography implies that as of 2006 designing the photomask for a given chip required ~100 CPU years of processing, and presumably that has only gone up.
Etching a 22nm line with 193nm light is a hard problem, and a lot of the techniques used certainly appear to require huge amounts of processing. It’s close to impossible to say how much of a bottle neck this particular step in the process is, but based on how much really knowing what is going on in even just simple mechanical design requires lots of simulation I would actually expect that every step in chip design has similar types of simulation requirements.
Yes, but how much of the work that goes into the next generation is just layout? It doesn’t solve all of your chemical or quantum mechanical issues, or fixes your photomasks for the next shrunken generation, etc. If layout were a major factor, we should expect to hear of ‘layout farms’ or supercomputers or datacenters devoted devoted to the task. I, at least, haven’t. (I’m sure Intel has a datacenter or two, but so do many >billion tech multinationals.)
And if layout is just a fraction of the effort like 10%, then Amdahl’s law especially applies.
it doesn’t give many actual current details, but http://en.wikipedia.org/wiki/Computational_lithography implies that as of 2006 designing the photomask for a given chip required ~100 CPU years of processing, and presumably that has only gone up.
Etching a 22nm line with 193nm light is a hard problem, and a lot of the techniques used certainly appear to require huge amounts of processing. It’s close to impossible to say how much of a bottle neck this particular step in the process is, but based on how much really knowing what is going on in even just simple mechanical design requires lots of simulation I would actually expect that every step in chip design has similar types of simulation requirements.