Have you used system verilog or some other hardware description language? Your clunk model of the ripple adder looks suspiciously like verilog code I wrote to make a ripple adder in a class. I can’t recall enough deets to tell how different they are, but you might gain some insights from investigating.
Good point, HDLs do solve a very similar problem in similar ways. There’s probably useful analogies to mine there. Also I just realized that it’s been almost ten years since I last used verilog.
Have you used system verilog or some other hardware description language? Your clunk model of the ripple adder looks suspiciously like verilog code I wrote to make a ripple adder in a class. I can’t recall enough deets to tell how different they are, but you might gain some insights from investigating.
Good point, HDLs do solve a very similar problem in similar ways. There’s probably useful analogies to mine there. Also I just realized that it’s been almost ten years since I last used verilog.